1. Field of the Invention
The present invention relates generally to a non-volatile memory device. More particularly, the present invention relates to a method of erasing a non-volatile memory device.
A claim of priority is made to Korean Patent Application 2004-99954 filed on Dec. 1, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A non-volatile memory device is a memory device capable of maintaining stored data even when its power supply is interrupted. An example of a non-volatile memory device is flash memory. Flash memory can be broadly classified into two categories according to two distinct memory cell array structures. The two categories of flash memory include NAND flash memory and NOR flash memory.
A NOR flash memory device typically comprises a plurality of flash memory cells used to store data. A flash memory cell generally includes source and drain regions doped with N+ impurities formed on a P-type semiconductor substrate and a channel region interposed between the source and drain regions. In addition, a flash memory cell generally includes a floating gate and a control gate. The floating gate is typically formed on the channel region and a thin insulating layer of 100 Å or less is usually formed between the channel region and the floating gate. The control gate is formed on the floating gate and an insulating layer is formed between the floating gate and the control gate. For programming, erasing, and reading, predetermined bias voltages are applied to the source, drain, gate, and substrate of the flash memory cell.
A flash memory device is typically divided into sectors, wherein each sector comprises a plurality of memory cells. Within each sector, the substrate is electrically connected to all of the plurality of cells so that an erase operation can be performed on the whole sector at once, including all of its memory cells. During the erase operation, a voltage of about −10V is applied to each gate, and a voltage of about 6V is applied to the substrate.
A conventional method for erasing a NOR-type flash memory device comprises a pre-program step, a main erase step, and a post-program step.
The pre-program step involves programming all of the memory cells in a sector using the same bias voltages used in a normal programming operation. The purpose of doing this is so that none of the cells will experience “excessive erasing”, i.e., removing too many electrons from the floating gate, in the main erase step. The main erase step is then performed so that all of the flash memory cells in the sector assume a logic state “1”. The post-program operation is performed in order to correct the voltage level of memory cells that have been “excessively erased” in the main erase step. The post-program operation is performed in the same manner as the pre-program operation except for the voltage bias conditions.
In the conventional NOR-type flash memory device, the pre-program step, the main erase step, and the post-program step make up fifty percent, thirty percent, and twenty percent of the total erase time, respectively. In other words, the pre-program step and the post-program step make up seventy percent of whole erase time. As a result, the performance of NOR-type flash memory devices could be dramatically improved by reducing the portion of the erase time dedicated to the pre-program step and the post-program step.